Synchronous semiconductor memory device with a write latency control function
US5568445A · kind A · utility
82Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 2, 1995 |
| Grant date | Oct 22, 1996 |
| Priority date | — |
| Expiry date | Mar 2, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device for processing data in synchronization with a system clock applied from the exterior includes a circuit for generating a write latency control signal, a circuit for generating one active information enlarged signal from a plurality of active information signals generated in response to a column related control signal supplied from the exterior, and a circuit for holding internal operations of a column address counter, a burst length counter and a data transfer switching circuit for a prescribed time in which the active information enlarged signal is in an active state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.