Process for manufacturing a plural stacked leadframe semiconductor device
US5569625A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 1994 |
| Grant date | Oct 29, 1996 |
| Priority date | — |
| Expiry date | Nov 22, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor process includes a stage, a semiconductor chip which is mounted on the stage, a plurality of electrode members which are wire bonded to the semiconductor chip, where a first gap is formed between the stage and one electrode member and a second gap is formed between two electrode members, a plurality of leads including inner leads which are wire bonded to at least one of the semiconductor chip and the electrode members and electrically connected thereto, and a resin package which encapsulates the semiconductor chip, the stage, the electrode members and the inner leads by a resin. The resin fills the first and second gaps, so that the stage and the one electrode member are isolated and the two electrode members are isolated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.