Wafer scale burn-in apparatus and process
US5570032A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 1993 |
| Grant date | Oct 29, 1996 |
| Priority date | — |
| Expiry date | Aug 17, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49156
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus for wafer scale burn-in and testing of semiconductor integrated circuits and a method for its utilization. A wafer is mated to a printed circuit board which electrically contacts the pads on each die using small conductive pillars. Single precise alignment of entire wafer within apparatus allows for testing all the dice on the wafer in parallel, eliminating need to probe each die individually. The apparatus is fitted with heating elements and cooling channels to generate the necessary wafer temperatures for burn-in and testing. The method of utilization eliminates processing of defective dice beyond burn-in and test, thereby increasing throughput.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.