Method and apparatus for identifying faults within a system
US5570376A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 1994 |
| Grant date | Oct 29, 1996 |
| Priority date | — |
| Expiry date | Oct 5, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2257
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Lists of candidate faults within an integrated circuit are generated, for the purpose of fault diagnosis, by performing a partial intersection of fault lists output from a full-scan test such as a JTAG test. The fault lists represent all candidate faults which may be responsible for producing a mismatched bit between an output test vector and an expected test vector provided by the full-scan test. The partial intersection is performed by first determining the number of occurrences of each candidate fault within all lists associated with each mismatched bit. Then, only faults which occur at least a pre-selected number of times are selected. In this manner, lists of candidate faulty gates are generated based on the relative degree of intersection between fault sets. The lists of candidate faulty gates are input to an X-Y location tool which determines the physical location on the integrated circuit of each of the candidate faulty gates to facilitate the efficient examination of each of the candidate faulty gates by test personnel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.