Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models

US5572437A · kind A · utility

Assignee

• LSI Logic Corporation · US

Inventors

• Michael D. Rostoker · Ramona, US
• Carlos Dangelo · Los Gatos, US
• Owen S. Bair · Saratoga, US

Key dates

• Filing date: May 20, 1994
• Grant date: Nov 5, 1996
• Expiry date: May 20, 2014

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/3308
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

An automatic logic-model generation system operates on a behavioral description of an electronic design (e.g., a circuit, a system, etc.) to automatically generate a low-level (i.e., circuit-level) design of the electronic design, to lay out the electronic design for production in the form of an integrated circuit, and to produce logic-level models incorporating accurate timing (and delay) information. A verification process is also performed whereby the logic-level model is automatically verified for accuracy.