Low cycle time CMOS process

US5573962A · kind A · utility

Assignee

• VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION · TW

Inventor

• Janmye Sung · Taipei, TW

Key dates

• Filing date: Dec 15, 1995
• Grant date: Nov 12, 1996
• Expiry date: Dec 15, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002

Abstract

A process for fabricating CMOS devices has been developed, in which decreased cycle time has been achieved, via a reduction in photomasking steps. The low cycle time CMOS process features the use of only one photo mask to create both the lightly doped, as well as the heavily doped N type, source and drain regions, by performing both implantations, after creation of the insulator sidewall spacer. In addition the P type source and drain regions are formed, using an oxide layer as a blockout for the P well region, thus eliminating the use of another photomasking procedure.