Sloped storage node for a 3-D dram cell structure
US5573979A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 1995 |
| Grant date | Nov 12, 1996 |
| Priority date | — |
| Expiry date | Feb 13, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/978
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Generally, the present invention utilizes dry plasma etching techniques such as Electron Cyclotron Resonance (ECR) to produce sloped sidewalls on a DRAM storage cell. The rounded corners of the lower electrode made by this technique allow the advanced dielectric material to be deposited without substantial cracking, and it also allows the capacitance to be closely predicted and controlled due to the uniformity in which the advanced dielectric layer can be fabricated. One embodiment of the present invention is method of making a microelectronic structure comprising a supporting layer (e.g. Si substrate 30) having a principal surface, a lower electrode overlying the principal surface of the supporting layer, and a high-dielectric-constant material layer (e.g. BST 44) overlying the top surface of the lower electrode. The lower electrode comprises a barrier layer (e.g. TiN 36), and an unreactive layer (e.g. Pt 42).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.