Self-aligned buried channel/junction stacked gate flash memory cell
US5574685A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 1, 1994 |
| Grant date | Nov 12, 1996 |
| Priority date | — |
| Expiry date | Sep 1, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/685
Abstract
An improved one-transistor flash EEPROM cell structure and a method for making the same is provided so that the effective channel length dimension is independent of the critical dimensions of the stacked gate structure. The cell structure (210) includes an n.sup.- buried channel/junction region (216) which is implanted in a substrate (212) before formation of a tunnel oxide (226) and a stacked gate structure (234). After the formation of the stacked gate structure, a p-type drain region (222) is implanted with a large tilt angle in the substrate. Thereafter, n.sup.+ source and n.sup.+ drain regions (218, 224) are implanted in the substrate so as to be self-aligned to the stacked gate structure. The cell structure of the present invention facilitates scalability to small size and is useful in high density application.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.