Polishing pad cluster for polishing a semiconductor wafer
US5575707A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 1994 |
| Grant date | Nov 19, 1996 |
| Priority date | — |
| Expiry date | Oct 11, 2014 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB24D7/06
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
A polishing pad cluster for polishing a semiconductor wafer having multiple integrated circuit dies includes a pad support and multiple polishing pads. Each pad has a polishing area substantially smaller than the wafer but not substantially smaller than an individual one of the integrated circuit dies. Each polishing pad is mounted to a respective polishing pad mount, which is in turn supported by the support. Each mount includes a respective joint having at least two degrees of freedom to allow the associated polishing pad to articulate with respect to the support to conform to the wafer. Each mount is substantially rigid in a direction perpendicular to the pad toward the pad support, and in some cases the adjacent mounts are completely isolated from one another. A magnet is used to bias the polishing pad against the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.