Method for making an EEPROM with thermal oxide isolated floating gate
US5576233A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 1995 |
| Grant date | Nov 19, 1996 |
| Priority date | — |
| Expiry date | Jun 21, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/35
Abstract
A method for making an EEPROM (10) in a semiconductor substrate (40) and EEPROM made according to the method includes forming a gate dielectric (38), such as oxide, nitride, multilayer dielectric, or the like, on a surface of the substrate (40) and forming a polysilicon floating gate (19) on the gate dielectric (38). A control gate (25) is formed at least partially overlying the floating gate (19), and a thermal oxide layer (56) is formed on the floating gate (19) in regions that are not covered by the control gate. Thus, the thermal oxide layer (56) encases any regions of the floating gate (19) uncovered by the control gate (25) and serves as a high quality dielectric to isolate the floating gate (19) from charge loss and other deleterious effects. Then, source and drain regions (21,27) are formed in the substrate (40).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.