Wafer-scale integrated circuit interconnect structure architecture
US5576554A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 10, 1993 |
| Grant date | Nov 19, 1996 |
| Priority date | — |
| Expiry date | Dec 10, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for substrate scale integration by interconnecting a large number of separate memory (or other circuit) modules on a semiconductor substrate so as to electrically exclude both defective modules and defective interconnect/power segments, and include operative modules and interconnect/power segments. A set of discretionary connections are associated with each of the separate modules and interconnect/power segments and such connections are made (or broken) after a module or interconnect or power segment is tested. A power supply network is set up by combining operative power segments. A bidirectional bus is set up by combining operative interconnect segments to connect to each operative modules. This bidirectional bus consists of one or more hierarchies for speed, power and yield considerations. Each module is assigned an identity code using discretionary connections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.