XOR CMOS logic gate
US5576637A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 1995 |
| Grant date | Nov 19, 1996 |
| Priority date | — |
| Expiry date | May 15, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An exclusive OR circuit includes a first series circuit in which a source of a first pMIS transistor is connected to a positive-voltage power supply line. A drain of the first pMIS transistor is connected to a drain of a first nMIS transistor via a second nMIS transistor. The source of the first nMIS transistor is connected to a low-voltage power supply line via a fourth nMIS transistor. A second series circuit has a drain of a third nMIS transistor connected to a high-voltage power supply line via a second pMIS transistor. The source of the third nMIS transistor is connected to the source of a third pMIS transistor. The drain of the third pMIS transistor is connected to the low-voltage power supply line via a fourth pMIS transistor. The gates of the first and third nMIS transistors and the first and third pMIS transistors are connected to one another and provided with a first input. The gates of the second and fourth nMIS transistors and the second and fourth pMIS transistors are connected to one another and provided with a second input. The sources of the second and third nMIS transistors are connected to each other and provide the exclusive OR of the first and second inputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.