Programmable hold delay
US5577214A · kind A · utility
14Cited by
17References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 23, 1995 |
| Grant date | Nov 19, 1996 |
| Priority date | — |
| Expiry date | May 23, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An EISA-compatible computer system having an arbitration mechanism which incorporates a programmable hold delay register and counter for delaying a CPU hold request (DHOLD) by a programmable number of BCLK cycles after an EISA device wins the top level and CPU/EISA level arbitration. The CPU hold request is not delayed if a DMA/ISA device wins the arbitration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.