Method for decreasing penalty resulting from a cache miss in multi-level cache system
US5577227A · kind A · utility
Inventors
Key dates
| Filing date | Aug 4, 1994 |
| Grant date | Nov 19, 1996 |
| Priority date | — |
| Expiry date | Aug 4, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system includes a processor, a main memory, a first level cache and a second level cache. The second level cache contains data lines. The first level cache contains data line fragments of data lines within the second level cache. In response to a processor attempt to access a data word, a cache controller searches for the data word in the first level cache. When a first level cache miss results from the attempted access, a search is made for the data word in the second level cache. When a second level cache miss results a new data line, which contains the data word, is fetched from the main memory. Concurrently, the cache controller determines which entries of the first level cache are invalid. Once the new data line is fetched from the main memory, the new data line is placed in the second level cache, replacing the second level victim cache line. In addition, as many data line fragments as possible from the new data line are placed into invalid entries in the first level cache. One of data line fragments from the new data line placed into the first level cache includes the data word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.