Digital circuit for performing multicycle addressing in a digital memory
US5577228A · kind A · utility
5Cited by
6References
4Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Dec 8, 1994 |
| Grant date | Nov 19, 1996 |
| Priority date | — |
| Expiry date | Dec 8, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The architecture of the cache memory of the present invention includes a data RAM, a TAG RAM, a controller and pad logic on a single integrated circuit chip. The cache memory is coupled to a CPU and a memory bus controller over a host bus. The host bus receives read data from the cache memory and provides write data to the cache memory. The cache memory controller provides signals to the memory bus controller to indicate whether data accessed by the CPU resides in the cache memory. The present invention increases memory speed by allowing circuit elements in the cache memory to operate during both phases of a system clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.