Patrick Chuang
41Patents
21h-index
31Co-inventors
85Inventor score
Filing activity: Oct 9, 1981 → Oct 28, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US4928260A | Content addressable memory array with priority encoder | Physics | 99 | Expired |
| US4611309A | Non-volatile dynamic RAM cell | Physics | 34 | Expired |
| US7313040B2 | Dynamic sense amplifier for SRAM | Physics | 31 | Expired |
| US4890260A | Content addressable memory array with maskable and resettable bits | Physics | 30 | Expired |
| US4421996A | Sense amplification scheme for random access memory | Electricity | 29 | Expired |
| US4634894A | Low power CMOS reference generator with low impedance driver | Physics | 28 | Expired |
| US7646215B2 | Efficient method for implementing programmable impedance output drivers and programmable input on die termination on a bi-directional data bus | Electricity | 28 | Active |
| US4888731A | Content addressable memory array system with multiplexed status and command information | Physics | 28 | Expired |
| US9494647B1 | Systems and methods involving data inversion devices, circuitry, schemes and/or related aspects | Physics | 27 | Active |
| US9679631B2 | Systems and methods involving multi-bank, dual- or multi-pipe SRAMs | Physics | 27 | Active |
| US9196324B2 | Systems and methods involving multi-bank, dual- or multi-pipe SRAMs | Physics | 25 | Active |
| US9853633B1 | Systems and methods involving lock-loop circuits, clock signal alignment, phase-averaging feedback clock circuitry | Electricity | 25 | Active |
| US7389457B2 | Shift registers free of timing race boundary scan registers with two-phase clock control | Physics | 25 | Active |
| US7595657B2 | Dynamic dual control on-die termination | Electricity | 25 | Active |
| US10659058B1 | Systems and methods involving lock loop circuits, distributed duty cycle correction loop circuitry | Physics | 24 | Active |
| US9935635B2 | Systems and methods involving pseudo complementary output buffer circuitry/schemes, power noise reduction and/or other features | Electricity | 24 | Active |
| US10425070B2 | Systems and methods involving lock-loop circuits, clock signal alignment, phase-averaging feedback clock circuitry | Electricity | 24 | Active |
| US9613670B2 | Memory systems and methods involving high speed local address circuitry | Physics | 24 | Active |
| US9318174B1 | Memory systems and methods involving high speed local address circuitry | Physics | 24 | Active |
| US8542050B2 | Minimized line skew generator | Physics | 24 | Active |
| US4438346A | Regulated substrate bias generator for random access memory | Physics | 23 | Expired |
| US10770133B1 | Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits | Physics | 19 | Active |
| US5121013A | Noise reducing output buffer circuit with feedback path | Electricity | 19 | Expired |
| US10854284B1 | Computational memory cell and processing array device with ratioless write port | Physics | 15 | Active |
| US10891076B1 | Results processing circuits and methods associated with computational memory cells | Physics | 13 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.