Vertical load resistor SRAM cell
US5578854A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 1995 |
| Grant date | Nov 26, 1996 |
| Priority date | — |
| Expiry date | Aug 11, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An SRAM cell consisting of a cross coupled transistors, a pair of transfer gate transistors and, a pair of load resistors, loading the cross-coupled transistors. Where soft error immunity is desired, the SRAM cell has a buried oxide layer isolating the devices from the silicon substrate. The load resistor is integrated into a contact stud, connecting a diffusion region of the SRAM cell to a power supply. An opening, in an insulating layer overlying the substrate and in contact with parts of the transistors including some diffusion regions, exposes a selected diffusion region of the SRAM cell. The contact stud with an integral resistor, consists of a core of a conductive material, and a highly resistive thin layer between the conducting core and the sides of the opening in the insulator and the selected contact areas. The conductive layer and the resistive layer are nearly planar with the top of the insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.