IC tester
US5579251A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 29, 1993 |
| Grant date | Nov 26, 1996 |
| Priority date | — |
| Expiry date | Nov 29, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31937
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Each of test channels CH.sub.1 --CH.sub.N includes a level/timing comparator section 20.sub.1 -20.sub.N for making a logic decision on the level of an input signal at strobes STRB1 and STRB2, and a logic comparator section 30.sub.1 -30.sub.N for making a logic comparison between the result of the logic decision and an expected value signal EXP.sub.1 -EXP.sub.N to output or inhibit the result of the logic comparison in accordance with comparison control signals CPE1, CPE2. Further, there are provided mode switching circuits 8.sub.1 -8.sub.N and mode switching signal generators 13.sub.1 -13.sub.N. Each of the mode switching circuits alters the comparison control signals CPE1, CPE2 as desired by mode switching signals CONT1, CONT2 and CONT3 of the corresponding test channels and logic operations, and controls whether or not to apply the altered comparison control signals to the corresponding logic comparator sections 30.sub.1 -30.sub.N in accordance with the pin control signals of the corresponding test channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.