Memory redundancy circuit
US5579265A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 1995 |
| Grant date | Nov 26, 1996 |
| Priority date | — |
| Expiry date | Feb 27, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure pertains to a memory redundancy circuit. A main memory may, if there should be defective zones (defective columns for example), be replaced by a redundancy memory. A defective address memory is initialized during the testing of the main memory. During normal operation relating to access to the main memory, each main memory address is compared with all the defective addresses to replace the zone of the main memory with a redundancy memory. During the testing of the main memory, it is generally necessary to initialize each address of the defective address memory. This causes time to be lost if the main memory is fault-free. The disclosure provides for an inhibition circuit that can be used to put the defective address memory out of service or to make its operation ineffective, and to do so permanently. Application to integrated circuit memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.