Semiconductor memory device and method for gating the columns thereof
US5579280A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1995 |
| Grant date | Nov 26, 1996 |
| Priority date | — |
| Expiry date | Jun 2, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor memory device with a block write function for reading and writing data in a unit of two bytes, which comprises a plurality of memory cell blocks for associating bits accessed in response to a column address to designate the upper one of the two bytes and bits accessed in response to a column address to designate the lower one of the two bytes, at least two column select lines enabled in response to same column addresses, and a control circuit for separately controlling the two column select lines, wherein the bits of the upper and lower bytes stored in the memory cell blocks are all outputted in response to the column addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.