Method and structure for use in static timing verification of synchronous circuits
US5579510A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 1993 |
| Grant date | Nov 26, 1996 |
| Priority date | — |
| Expiry date | Jul 21, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A universal synchronization element is used in a static timing verification system to represent selected combinational primitive elements, synchronous primitive elements and external primitive elements in the user's synchronous digital circuit. Each of these digital circuit element in a user's digital circuit design is represented by a corresponding universal synchronization element having a propagation time characteristic equivalent to the digital circuit element and a stable time characteristic equivalent to the digital circuit element. The propagation and stable time characteristics are defined in relation to a clock signal for the digital circuit element in the user's circuit that the universal synchronization element represents. The universal synchronization element does not a fixed timing relationship between the signals on its input and output terminals. The adjustment of stable interval starting and end times and the propagation interval starting and end times is sufficient to represent the timing characteristics of circuit element with the universal synchronization element of this invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.