Trench depletion MOSFET
US5581100A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 30, 1994 |
| Grant date | Dec 3, 1996 |
| Priority date | — |
| Expiry date | Aug 30, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/127
Abstract
A vertical trench power MOS transistor with low on-resistance is obtained by eliminating the inversion region of a conventional structure. In one embodiment, a deep-depletion region is formed between the trench gates to provide forward blocking capability. In another embodiment, forward blocking is achieved by depletion from the trench gates and a junction depletion from a P diffusion between the gates. Both embodiments are preferably fabricated in a cellular geometry. The device may also be provided in a horizontal conduction configuration in which the MOS gate is disposed on the upper surface of the semiconductor wafer over the deep-depletion region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.