Carry skip adder with enhanced grouping scheme
US5581497A · kind A · utility
13Cited by
12References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 17, 1994 |
| Grant date | Dec 3, 1996 |
| Priority date | — |
| Expiry date | Oct 17, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/506
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An adder is described. The adder generates a block generate signal after one domino gate delay. The adder can also generate a carry out signal, generate a first plurality of sum signals in response to the carry out signal, generate a block generate signal, generate a group generate signal, and generate a second plurality of sum signals in response to the carry out signal, block generate signal and group generate signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.