Stack of IC chips in lieu of single IC chip
US5581498A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 1994 |
| Grant date | Dec 3, 1996 |
| Priority date | — |
| Expiry date | Oct 20, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic package is disclosed in which a plurality of stacked "same function" IC chips are designed to be used in lieu of a single IC chip, and to fit into a host computer system, in such a way that the system is "unaware" that substitution has been made. Memory packages are of primary interest, but other packages are also feasible, such as packages of FPGA chips. In order to "translate" signals between the host system and the stacked IC chips, it is necessary to include suitable interface circuitry between the host system and the stacked chips. Specific examples are disclosed of a 4 MEG SRAM package containing 4 stacked IC chips each supplying a 1 MEG memory, and of 64 MEG DRAM packages containing 4 stacked IC chips each supplying a 16 MEG memory. The interface circuitry can be provided by a single special purpose IC chip included in the stack, referred to as a VIC chip, which chip provides both buffering and decoding circuitry. Additionally, the VIC chip should provide power supply buffering. And, if it has sufficient real estate, such performance enhancing functions as error correction, memory cache, and synchronized memory may be included in the VIC chip circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.