Method for reading a non-volatile memory array
US5581502A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 1995 |
| Grant date | Dec 3, 1996 |
| Priority date | — |
| Expiry date | May 2, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device is provided having an array of single transistor memory cells read in accordance with an improved read cycle operation. That is, a selected cell mutually connected via a single bit line to other cells is assured activation necessary to discern a programmed or unprogrammed state of that cell. The non-selected cells connected to the selected cell are advantageously assured of non-activation by applying a negative voltage to the word lines associated with those cells. The negative voltage is less than the threshold voltage associated with the single transistor MOS device. The non-selected cells are thereby retained inactive to provide a singular active or inactive selected cell dependent solely upon the programmed state of the array. Negative voltage upon the non-selected cells provides minimal leakage of over-erased cells normally associated with depletion mode operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.