Non-volatile electrically erasable memory with PMOS transistor NAND gate structure
US5581504A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 14, 1995 |
| Grant date | Dec 3, 1996 |
| Priority date | — |
| Expiry date | Nov 14, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND Flash EEPROM string is formed in a common N-well and includes a plurality of P-channel MOS stacked-gate storage transistors and P-channel MOS string and ground select transistors. In the preferred embodiment, each P-channel storage transistor is programmed via hot electron injection from the depletion region proximate its P+ drain/N-well junction and erased via electron tunneling from its floating gate to its P-type channel as well as to its P+ source and P+ drain regions without requiring high programming and erasing voltages, respectively. Further, high P/N junction biases are not required during programming or erasing operations. This allows the dimensions of the present embodiments to be reduced to a size smaller than that of comparable conventional N-channel NAND Flash EEPROM strings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.