Fully depleted lateral transistor

US5583365A · kind A · utility

Assignee

• SGS-Thomson Microelectronics S.A. · IT

Inventors

• Flavio Villa · Milano, IT
• Enrico M. A. Ravanelli · Monza, IT

Key dates

• Filing date: Feb 23, 1994
• Grant date: Dec 10, 1996
• Expiry date: Feb 23, 2014

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S148/126

Abstract

The breakdown characteristics of a lateral transistor integrated in an epitaxial layer of a first type of conductivity grown on a substrate of an opposite type of conductivity and comprising a drain region formed in said epitaxial layer, are markedly improved without recurring to critical adjustments of physical parameters of the integrated structure by forming a buried region having the same type of conductivity of the substrate and a slightly higher level of doping at the interface between the epitaxial layer and the substrate in a zone laying beneath the drain region of the transistor.