Floating-point processor having post-writeback spill stage
US5583805A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1994 |
| Grant date | Dec 10, 1996 |
| Priority date | — |
| Expiry date | Dec 9, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49915
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for handling special cases outside of normal floating-point arithmetic functions is provided that is used in a floating-point unit used for calculating arithmetic functions. The floating-point unit generates an exponent portion and a mantissa portion and a writeback stage is coupled to the exponent portion and to the mantissa portion and is specifically used to handle the special cases outside the normal float arithmetic functions. A spill stage is also provided and is coupled to the writeback stage to receive a resultant exponent and mantissa. A register file unit is coupled to the writeback stage and the spill stage through a plurality of rename busses, which are used to carry results between the writeback stage and spill stage and the register file. The spill stage is serially coupled to the writeback stage so as to provide a smooth operation in the transition of operating on the results from the writeback stage for the exponent and mantissa. Each rename bus has a pair of tri-state buffers, one used to couple the rename bus to the writeback stage and the other used to couple the rename bus to the spill stage. The instruction dispatcher also provides location informa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.