Transistor structure for erasable and programmable semiconductor memory devices
US5583811A · kind A · utility
13Cited by
9References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 13, 1994 |
| Grant date | Dec 10, 1996 |
| Priority date | — |
| Expiry date | Jul 13, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable EEPROM cell structure consisting in a split-gate structure in series with a coupling capacitor between the floating gate and an additional program gate in order to provide enhanced injection efficiency. The electron injection is controlled by a control gate at the source side. The area of the coupling capacitor is selected with a substantial coupling factor to a high voltage onto the floating gate during programming so as to produce hot-electron injection at the split point in the channel region between the control gate and the floating gate. Submicrosecond programming at a 5 V drain voltage can thereby be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.