Method of fabricating a thin film transistor
US5585292A · kind A · utility
6Cited by
1References
10Claims
0Family size
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Key dates
| Filing date | Feb 3, 1995 |
| Grant date | Dec 17, 1996 |
| Priority date | — |
| Expiry date | Feb 3, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6739
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thin film transistor comprises an insulator interposed between a gate electrode and a polycrystalline silicon semiconductor layer, with the polycrystalline silicon semiconductor layer having a source region and a drain region with a channel between the source region and the drain region. The insulator comprises an ONO structure having an interfacial oxide layer in contact with the polycrystalline silicon semiconductor layer, a cap oxide layer in contact with the gate electrode, and a nitride layer interposed between the interfacial oxide layer and the nitride layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.