Synchronous address latching for memory arrays
US5586081A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 1995 |
| Grant date | Dec 17, 1996 |
| Priority date | — |
| Expiry date | May 23, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Synchronous address latching circuitry for a memory device having at least first and second banks of memory arrays is described. The latching circuitry has a master latch to receive and store an external address. A first slave latch is also included to receive and store the external address from the master latch if the external address belongs to the first bank and to provide the external address as a first address to the first bank. A second slave latch is included to receive and store the external address from the master latch if the external address belongs to the second bank and to provide the external address as a second address to the second bank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.