Richard E. Fackenthal
90Patents
11h-index
41Co-inventors
78Inventor score
Filing activity: Jun 3, 1994 → Sep 18, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6870767B2 | Variable level memory | Physics | 85 | Expired |
| US6643169B2 | Variable level memory | Physics | 82 | Expired |
| US7356755B2 | Error correction for multi-level cell memory with overwrite capability | Physics | 79 | Expired |
| US5497355A | Synchronous address latching for memory arrays | Physics | 49 | Expired |
| US6549457B1 | Using multiple status bits per cell for handling power failures during write operations | Physics | 36 | Expired |
| US7577024B2 | Streaming mode programming in phase change memories | Physics | 33 | Active |
| US8605490B2 | Non-volatile SRAM cell that incorporates phase-change memory into a CMOS process | Physics | 23 | Active |
| US5586081A | Synchronous address latching for memory arrays | Physics | 19 | Expired |
| US10431281B1 | Access schemes for section-based data protection in a memory device | Electricity | 14 | Active |
| US9336875B2 | Memory systems and memory programming methods | Physics | 13 | Active |
| US6748482B1 | Multiple non-contiguous block erase in flash memory | Physics | 12 | Expired |
| US8977929B2 | Rearranging write data to avoid hard errors | Physics | 11 | Active |
| US5563843A | Method and circuitry for preventing propagation of undesired ATD pulses in a flash memory device | Physics | 11 | Expired |
| US9837151B2 | Memory systems and memory programming methods | Physics | 11 | Active |
| US6625716B2 | Method apparatus, and system for efficient address and data protocol for a memory | Physics | 10 | Expired |
| US7940553B2 | Method of storing an indication of whether a memory location in phase change memory needs programming | Physics | 9 | Active |
| US7848138B2 | Biasing a phase change memory device | Physics | 8 | Active |
| US7518934B2 | Phase change memory with program/verify function | Physics | 8 | Active |
| US10311953B2 | Memory systems and memory programming methods | Physics | 7 | Active |
| US10403389B2 | Array plate short repair | Physics | 7 | Active |
| US10416903B2 | Wear leveling | Physics | 6 | Active |
| US7885099B2 | Adaptive wordline programming bias of a phase change memory | Emerging Cross-Sectional Technologies | 5 | Active |
| US10855295B2 | Access schemes for section-based data protection in a memory device | Electricity | 5 | Active |
| US9941021B2 | Plate defect mitigation techniques | Physics | 4 | Active |
| US11348928B1 | Thin film transistor random access memory | Electricity | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.