Triple register RISC digital signal processor
US5586284A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 1995 |
| Grant date | Dec 17, 1996 |
| Priority date | — |
| Expiry date | Oct 23, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/355
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The STREAMER FOR RISC DIGITAL SIGNAL PROCESSOR shown herein allows a CPU 46 to interface with a memory 60 via data registers 50. Pre-fetch and post-store of the correct address is determined by an address generator 58 according to a rule determined by a context register 52. An index indicative of this address is stored in an index register 54. The data, context, and index registers together form a streamer 56, streaming data between the CPU 46 and data memory 60. The rule of the context register 52 also drives a converter 62 for converting data between memory format and register format. The speed and flexibility of a RISC device is combined with the intensive memory access of a digital signal processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.