Partial cache line write transactions in a computing system with a write back cache
US5586297A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 1994 |
| Grant date | Dec 17, 1996 |
| Priority date | — |
| Expiry date | Mar 24, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0886
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system is presented which includes a memory, an input/output adapter and a processor. The processor includes a write back cache in which dirty data may be stored. When performing a coherent write from the input/output adapter to the memory, a block of data is written from the input/output adapter to a memory location within the memory. The block of data contains less data than a full cache line in the write back cache. The write back cache is searched to determine whether the write back cache contains data for the memory location. When the search determines that the write back cache contains data for the memory location a full cache line which contains the data for the memory location is purged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.