Method of making flash memory cell
US5587332A · kind A · utility
53Cited by
18References
43Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 1, 1992 |
| Grant date | Dec 24, 1996 |
| Priority date | — |
| Expiry date | Sep 1, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/49
Abstract
The present invention relates to a flash EEPROM cell using polysilicon-to-polysilicon hot electron emission to erase the memory contents of the cell. Exemplary embodiments include a side gate, a control gate, a floating gate and source and drain regions. Appropriate biasing of these gates and source and drain regions controls the electron population of the floating gate. The memory cells may be of either the double polysilicon or triple polysilicon variety. Peripheral transistors are formed from a last formed polysilicon layer to avoid degrading the peripheral transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.