Process for manufacturing a stacked integrated circuit package
US5587341A · kind A · utility
56Cited by
7References
17Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Oct 18, 1994 |
| Grant date | Dec 24, 1996 |
| Priority date | — |
| Expiry date | Oct 18, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1572
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.