DMA controller for memory scrubbing
US5588112A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 1996 |
| Grant date | Dec 24, 1996 |
| Priority date | — |
| Expiry date | Feb 20, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/106
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault tolerant computer system is described in which a direct memory access controller examines the check bit data on every data element that is accessed by the system. The address of any data element that is found to have an error in the check bit data is stored by the direct memory access controller, the check bit data is used by the direct memroy access controller to correct the error, and the corrected data element is rewritten to the original storage address. By the use of this arrangement, the central processing unit or units of the computer system are free to perform other tasks, thus improving system throughput, and preventing the accumulation of data element errors in the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.