Method and apparatus for synchronizing data queues in asymmetric reflective memories
US5588132A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 20, 1994 |
| Grant date | Dec 24, 1996 |
| Priority date | — |
| Expiry date | Oct 20, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/546
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A network of processors synchronize modification of a common data structure stored in an asymmetric reflective memory by using a queue. A first processor stores a queue element in a global write-only address space of the reflective memory, the reflective memory to copy the queue element to a local read/write address space of a second processor. The first processor also stores a queue header in the global write-only address space. In response to detecting the queue element, the second processor reads the queue header and then overwrites the queue header with a zero. The reading and writing of the queue header are performed atomically in the local read/write address space of the second processor. The second processor processes the queue element, and marks the queue element as processed in the global address space of the reflective memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.