Method and arrangement for clock adjustment using programmable period binary rate multiplier
US5588145A · kind A · utility
2Cited by
7References
51Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 31, 1995 |
| Grant date | Dec 24, 1996 |
| Priority date | — |
| Expiry date | Mar 31, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and arrangement for adjusting a clock frequency to allow computer devices with different clock frequencies to operate together. The arrangement scales the input clock frequency to be scaled by any desired fraction by controlling both the numerator and denominator of the scaling fraction. Clock frequency adjustment is achieved by transforming the input clock frequency into a periodic clock frequency that is reset following a desired clock period and scaling this periodic clock frequency according to a desired divisor value to generate the desired clock frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.