John A. Wishneusky
23Patents
10h-index
16Co-inventors
72Inventor score
Filing activity: Oct 25, 1978 → Aug 26, 2010
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7653757B1 | Method for using a multi-master multi-slave bus for power management | Physics | 131 | Expired |
| US5765023A | DMA controller having multiple channels and buffer pool having plurality of buffers accessible to each channel for buffering data transferred to and from host computer | Physics | 47 | Expired |
| US7793005B1 | Power management system using a multi-master multi-slave bus and multi-function point-of-load regulators | Electricity | 36 | Active |
| US8239597B2 | Device-to-device communication bus for distributed power management | Electricity | 36 | Active |
| US7685320B1 | Autonomous sequencing and fault spreading | Physics | 35 | Expired |
| US4975828A | Multi-channel data communications controller | Physics | 30 | Expired |
| US5781799A | DMA controller arrangement having plurality of DMA controllers and buffer pool having plurality of buffers accessible to each of the channels of the controllers | Physics | 29 | Expired |
| US4254477A | Reconfigurable memory circuit | Physics | 16 | Expired |
| US8452897B1 | Method for using a multi-master multi-slave bus for power management | Physics | 15 | Active |
| US6901507B2 | Context scheduling | Physics | 15 | Expired |
| US5566352A | Register-read acknowledgment and prioritization for integration with a hardware-based interrupt acknowledgment mechanism | Physics | 10 | Expired |
| US7908402B2 | Integrated multi-function point-of-load regulator circuit | Electricity | 8 | Active |
| US7426215B2 | Method and apparatus for scheduling packets | Electricity | 8 | Active |
| US5864716A | Tagged data compression for parallel port interface | Emerging Cross-Sectional Technologies | 5 | Expired |
| US6874080B2 | Context processing by substantially simultaneously selecting address and instruction of different contexts | Physics | 3 | Expired |
| US6981113B2 | Storage registers for a processor pipeline | Physics | 2 | Expired |
| US6963535B2 | MAC bus interface | Electricity | 2 | Expired |
| US7415027B2 | Processing frame bits | Physics | 2 | Expired |
| US7522620B2 | Method and apparatus for scheduling packets | Electricity | 2 | Active |
| US6826676B2 | Extending immediate operands across plural computer instructions with indication of how many instructions are used to store the immediate operand | Physics | 2 | Expired |
| US7007156B2 | Multiple coprocessor architecture to process a plurality of subtasks in parallel | Physics | 2 | Expired |
| US5588145A | Method and arrangement for clock adjustment using programmable period binary rate multiplier | Physics | 2 | Expired |
| US7243214B2 | Stall optimization for an in-order, multi-stage processor pipeline which analyzes current and next instructions to determine if a stall is necessary | Physics | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.