Process for fabricating a non-silicided region in an integrated circuit

US5589423A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• Ted R. White · Austin, US
• Ting-Chen Hsu · Taichung, TW
• Bradley M. Somero · Austin, US
• Mark A. Chonko · Austin, US
• Jung-Hui Lin · Austin, US

Key dates

• Filing date: Oct 3, 1994
• Grant date: Dec 31, 1996
• Expiry date: Oct 3, 2014

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0212

Abstract

A process for the fabrication of a non-silicided region in an integrated circuit includes the fabrication of a silicide blocking layer (24, 46, 54, 92, 112). In one embodiment, a field transistor (80) is formed by depositing a silicide blocking layer (84) overlying a field gate electrode (70) and source and drain regions (76, 78). A carbonaceous mask (86) is formed on the silicide blocking layer (84) overlying the field transistor (80). A partial etching process is performed to remove a portion of the silicide blocking layer (84) exposed by the carbonaceous mask (86). Then, the carbonaceous mask (86) is removed and the etching process is continued to completely remove portions of the silicide blocking layer (84) not originally protected by the carbonaceous mask (86). The etching process forms a silicide blocking layer (92) overlying the field transistor (80) and sidewall (94) adjacent to an MOS gate electrode (68).