Ted R. White
44Patents
13h-index
43Co-inventors
81Inventor score
Filing activity: Jun 19, 1987 → Apr 17, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6838322B2 | Method for forming a double-gated semiconductor device | Electricity | 176 | Expired |
| US7226833B2 | Semiconductor device structure and method therefor | Electricity | 122 | Expired |
| US6831350B1 | Semiconductor structure with different lattice constant materials and method for forming the same | Electricity | 78 | Expired |
| US7018901B1 | Method for forming a semiconductor device having a strained channel and a heterojunction source/drain | Electricity | 65 | Expired |
| US5918147A | Process for forming a semiconductor device with an antireflective layer | Electricity | 58 | Expired |
| US7494856B2 | Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor | Electricity | 49 | Active |
| US7282402B2 | Method of making a dual strained channel semiconductor device | Electricity | 42 | Expired |
| US7074664B1 | Dual metal gate electrode semiconductor fabrication process and structure thereof | Electricity | 40 | Expired |
| US5589423A | Process for fabricating a non-silicided region in an integrated circuit | Electricity | 34 | Expired |
| US7067868B2 | Double gate device having a heterojunction source/drain and strained channel | Electricity | 28 | Expired |
| US4902533A | Method for selectively depositing tungsten on a substrate by using a spin-on metal oxide | Electricity | 28 | Expired |
| US7037795B1 | Low RC product transistors in SOI semiconductor process | Electricity | 19 | Expired |
| US7226820B2 | Transistor fabrication using double etch/refill process | Electricity | 16 | Expired |
| US7803670B2 | Twisted dual-substrate orientation (DSO) substrates | Electricity | 13 | Active |
| US7029980B2 | Method of manufacturing SOI template layer | Emerging Cross-Sectional Technologies | 13 | Expired |
| US7205210B2 | Semiconductor structure having strained semiconductor and method therefor | Electricity | 13 | Expired |
| US7288458B2 | SOI active layer with different surface orientation | Electricity | 12 | Expired |
| US7524707B2 | Modified hybrid orientation technology | Electricity | 12 | Active |
| US7821067B2 | Electronic devices including a semiconductor layer | Electricity | 10 | Active |
| US7208357B2 | Template layer formation | Emerging Cross-Sectional Technologies | 9 | Expired |
| US8163615B1 | Split-gate non-volatile memory cell having improved overlap tolerance and method therefor | Electricity | 7 | Active |
| US7265004B2 | Electronic devices including a semiconductor layer and a process for forming the same | Electricity | 6 | Expired |
| US7749829B2 | Step height reduction between SOI and EPI for DSO and BOS integration | Electricity | 5 | Active |
| US8426310B2 | Method of forming a shared contact in a semiconductor device | Electricity | 5 | Active |
| US7163903B2 | Method for making a semiconductor structure using silicon germanium | Emerging Cross-Sectional Technologies | 5 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.