Method and structure for data integrity in a multiple level cache system
US5590310A · kind A · utility
11Cited by
10References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 21, 1995 |
| Grant date | Dec 31, 1996 |
| Priority date | — |
| Expiry date | Apr 21, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A structure and a method provide data integrity for a multiprocessor system having a cache memory and a snoop tag cache. In one embodiment, the snoop tag cache copies the tags of a primary cache. Whenever a write operation occurs, the snoop tag cache is accessed to determine if the accessed tag matches a predetermined portion of the address of the memory location on which the write operation is performed. If so, a signal is sent to the CPU associated with the primary cache so that the corresponding entries in the primary cache and the snoop tag cache can be invalidated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.