Combined multiprocessor interrupt controller and interprocessor communication mechanism
US5590338A · kind A · utility
15Cited by
15References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 8, 1995 |
| Grant date | Dec 31, 1996 |
| Priority date | — |
| Expiry date | Aug 8, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A combined multiprocessor interrupt controller and interprocessor communication mechanism includes a system bus, an input/output bridge element coupled to the system bus, and a system controller coupled to the system bus. The input/output bridge element includes circuitry for receiving interrupt requests, for obtaining processor-associated vectors, and for packaging obtained processor-associated vectors into interprocessor communication messages. The system controller includes circuitry for receiving and decoding interprocessor communication messages, and for providing processor-associated vectors to the associated processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.