Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices
US5592102A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1995 |
| Grant date | Jan 7, 1997 |
| Priority date | — |
| Expiry date | Oct 19, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17764
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic array integrated circuit has several regular columns of programmable logic circuitry and a spare column which includes a subset of the programmable logic circuitry that is included in a regular column. In the event of a defect in the circuitry in a regular column that is duplicated in the spare column, the regular column logic functions that are thus duplicated are shifted from column to column so that the spare column circuitry is put to use and the defective regular column circuitry is not used. Regular column functions that are not duplicated in the spare column are not shifted. Data for programming the columns is selectively routed to the columns with or without column shifting, depending on whether that data is for functions that are or are not duplicated in the spare column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.