Process for forming a semiconductor device including conductive members
US5593919A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 1995 |
| Grant date | Jan 14, 1997 |
| Priority date | — |
| Expiry date | Sep 5, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76897
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The embodiments of the present invention allow the formation of interconnect and vias without forming via veils or excessive thinning of vias. Conductive members (52, 54, 56, 58) are formed with a pattern generally corresponding to the shape of interconnects. A lower intermetallic insulating layer (70)is deposited over the substrate (30) and removed over conductive members (52, 54, 56, 58) before forming via portions. Via portions are formed from the conductive members (52, 54, 56, 58). An upper intermetallic insulating layer (134) is formed and planarized to fill locations overlying the interconnect portions of the conductive members (52, 54, 56, 58) near the vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.