Memory circuit with switch for selectively connecting an input/output pad directly to a nonvolatile memory cell
US5594694A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1995 |
| Grant date | Jan 14, 1997 |
| Priority date | — |
| Expiry date | Jul 28, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/48
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit operable in a test mode and a normal operating mode, which includes an improved test mode switch. In the test mode of preferred embodiments in which the circuit is an integrated memory chip, the test mode switch is closed so as to connect an input/output (I/O) pad directly with a selected memory cell (so a current/voltage characterization of the cell can be obtained). In the normal operating mode of these embodiments, the test mode switch is open and it isolates the I/O pad from direct connection with the selected cell even under the condition that a transistor of the test mode switch undesirably becomes conductive (e.g., due to low voltage on the I/O pad, inductive coupling, or the like). In preferred embodiments, the test mode switch includes a set of series-connected pass transistors and a isolation voltage switch, the pass transistors pass test signals (indicative of test data to be written to or read from a selected cell) directly between the I/O pad and the selected cell in the test mode, and no signals pass through the pass transistors between the I/O pad and any memory cell in the normal mode. In the normal mode of such preferred embodiments, data to b…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.