PCI split transactions utilizing dual address cycle
US5594882A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 4, 1995 |
| Grant date | Jan 14, 1997 |
| Priority date | — |
| Expiry date | Jan 4, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A scheme for providing split transaction capability on a PCI standard bus without modification to the existing PCI standard. Additional address bits are provided to a standard PCI address signal. The additional bits carry information regarding the requestor of a read transaction. By providing the requestor's identification to an addressed target, data is provided by the target device as a posted write. By using this enhanced mode, read requests need not be continually retried. If a target device is unable to respond to the enhanced address signal, the transaction is resent as a standard PCI address signal with the enhanced bits turned off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.