Method for fabricating a fully depleted lateral transistor
US5595921A · kind A · utility
5Cited by
6References
7Claims
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Key dates
| Filing date | Jun 2, 1995 |
| Grant date | Jan 21, 1997 |
| Priority date | — |
| Expiry date | Jun 2, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/126
Abstract
The breakdown characteristics of a lateral transistor integrated in an epitaxial layer of a first type of conductivity grown on a substrate of an opposite type of conductivity and comprising a drain region formed in said epitaxial layer, are markedly improved without recurring to critical adjustments of physical parameters of the integrated structure by forming a buried region having the same type of conductivity of the substrate and a slightly higher level of doping at the interface between the epitaxial layer and the substrate in a zone laying beneath the drain region of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.