Status register with asynchronous read and reset and method for providing same
US5596288A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 1995 |
| Grant date | Jan 21, 1997 |
| Priority date | — |
| Expiry date | Sep 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single bit status register includes an input flip-flop, an asynchronous latch having an input coupled to an output of the input flip-flop, a comparator for comparing the outputs of the flip-flop and the latch, and an output stage which provides an error output when the comparator determines that the outputs of the flip-flop and the latch are not the same. In this fashion, it is known when a "read" of the status register is invalid due to the presence of the error output. Preferably, the register also includes a reset disabling mechanism which prevents the input flip-flop from being reset until a valid read has occurred. A n-bit status register includes n register sections, where each register section includes an input flip-flop, an asynchronous latch having an input coupled to an output of the input flip-flop, and a register section comparison mechanism for comparing the outputs of the flip-flop and the latch in that register section. The method of the present invention includes the steps of: a) capturing a status bit in an input flip; b) latching the status bit into an output latch; c) asynchronously enabling the output latch; d) comparing the outputs of the flip-flop and the la…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.